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对射频接收机中双模分频器的设计和应用进行了研究.提出了一种改进型D-latch以提高双模分频器速度与驱动能力,一种将D-latch与“或”逻辑门集成的结构以降低电路的复杂度.采用TSMC0.18μm CMOS混合信号工艺实现了用于地面数字电视接收机的除16/17双模分频器.采用0.18μmCMOS标准单元库设计并以与双模分频器同样的工艺实现了可编程吞吐式脉冲分频器.测试结果显示双模分频器的输出抖动小于0.03%,而且能够与可编程吞吐式脉冲分频器良好地配合工作.
The design and application of dual-mode frequency divider in RF receiver are studied.An improved D-latch is proposed to improve the speed and driving ability of dual-mode divider, "Logic gate integrated structure to reduce the complexity of the circuit.Using TSMC0.18μm CMOS mixed-signal technology to achieve a 16/17 dual-mode divider for terrestrial digital television receiver.Using 0.18μmCMOS standard cell library design and to The same process as the dual-mode divider implements a programmable throughput pulse divider that shows the output of the dual-mode divider is less than 0.03% jitter and works well with a programmable throughput pulse divider .