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报导了一系列256k存贮器的设计,它们都将错误校正编码集成进存贮器结构中去。从简单的单一错误校正乘积码起,成功的设计在编码能力、存取延迟及通讯和计算的复杂性方面寻找折衷方案。在最有效的设计中,所有256k位被编制形成一个代码字,这是从一个摄影平面导出的双重错误校正和三重错误检测码。因为所有的位都是这个单一代码字的元素,所以编码效能很高,所需要的奇偶校验位仪增加了存贮容量的大约百分之三。单一的错误校正可以在读的时候进行,而只比通常无冗余的存贮器附加很少延迟时间。多个错误校正可以由存储器管理系统来进行。各种失效模式,包括组成64×64子矩阵之一的整个一列失效也是可以容许的。写入存储器包括一个读写周期,比般的存储器稍微慢一点。
A series of 256k memory designs are reported that incorporate error correction coding into the memory structure. From a simple single error correction product code, successful designs look for compromises in terms of encoding capabilities, access delays, and the complexity of communications and computations. In the most efficient design, all 256k bits are programmed to form a code word, which is a double error correction and triple error detection code derived from one photographic plane. Because all the bits are elements of this single codeword, the coding performance is high and the required parity checker adds about three percent of the storage capacity. A single error correction can be done at the time of reading, with only a little delay than usual non-redundant memory. Multiple error correction can be performed by the memory management system. Various failure modes, including failure of an entire column of one of the 64 × 64 sub-matrices, are also tolerable. Writing to memory includes a read and write cycle, a bit slower than normal memory.