论文部分内容阅读
实现一兆位DRAM需要解决的严重问题之一就是与数据线充、放电有关的功耗问题。为解决这一问题,本文提出了能使功耗减少大约1/4的三种方法:多路数据线结构、512刷新周期以及芯片电压限制电路。通过46平方毫米的实验性n-MOS1兆位DRAM芯片的设计和分析,证明这些方法是有效的。当周期时间为260毫微秒、快速存取时间为90毫微秒时,制作的1兆位DRAM芯片额定工作功耗是295毫瓦。还论述了进一步降低功耗的可能性。
One of the serious problems that need to be solved to realize one megabit DRAM is the power consumption problem related to charging and discharging of the data line. In order to solve this problem, this paper proposes three ways to reduce the power consumption by about 1/4: multiple data line structure, 512 refresh cycle and chip voltage limit circuit. The design and analysis of a 46 mm2 experimental n-MOS1 megabit DRAM chip prove that these methods are effective. When the cycle time of 260 nanoseconds, fast access time of 90 nanoseconds, the production of 1 megabit DRAM chip rated operating power is 295 milliwatts. It also discusses the possibility of further reducing power consumption.