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多级时钟树构造是解决时钟布线问题的关键。本文提出一种新的层次式布线策略，它将拓扑生成。绕障碍DME及BUFFER定位同时进行考虑，避免了布线的盲目性，减少了后处理工作。首先，对时钟汇点进行层次式均匀划分，在各个局部区域同时进行时钟子树的拓扑生成和DME嵌入：然后，根据各局部区域的布线情况，平衡各子树的负载和延迟，为各区域分配适当驱动能力的BUFFER。算法中的BUFFER定位是层次式的，有利于减少时钟偏差敏感度。实验表明，与将BUFFER插入作为后处理步骤相比，我们的算法在连线总长、延迟方面取得了明显的改善。
Multi-level clock tree structure is the key to solve the problem of clock routing. This paper presents a new hierarchical routing strategy that generates the topology. Around the obstacles DME and BUFFER positioning at the same time to consider, to avoid the blindness of the wiring, reducing post-processing work. First of all, the clock rendezvous is hierarchically and evenly divided, and the clock subtree topological generation and DME embedding are performed in each local area at the same time. Then, according to the routing of each local area, the load and delay of each subtree are balanced, Assign the appropriate drive capacity BUFFER. Algorithm BUFFER positioning is hierarchical, help to reduce the clock bias sensitivity. Experiments show that, compared with inserting BUFFER as a post-processing step, our algorithm has achieved a significant improvement in connection length and delay.