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This work proposes a Field Programmable Gate Array (FPGA)-oriented architecture for the IEEE 802. 11 Distributed Coordination Function (DCF) transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance (CSMA/CA), develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language (VHDL). The novelty of our proposal is twofold. Firstly, all MAC parameters (i.e., Max/Min Contention Window, Data Unit Length, Fragmentation Threshold, Retry Limit, etc.) can be directly accessed and programmed from the application layer interface, which is necessary to achieve better network performance in dynamic environments. Secondly, the character based on FPGA makes the proposal more flexible and risk-reduced for the development of DCF-based wireless networks, such as MANETs and software-defined-radio-based cognitive ad hoc networks.
This work proposes a Field Programmable Gate Array (FPGA) -oriented architecture for the IEEE 802.11 Distributed Coordination Function (DCF) transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance (CSMA / CA), develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language (VHDL). The novelty of our proposal is twofold. , Max / Min Contention Window, Data Unit Length, Fragmentation Threshold, Retry Limit, etc.) can be directly accessed and programmed from the application layer interface, which is necessary to achieve better network performance in dynamic environments. Secondly, the character based on FPGA makes the proposal more flexible and risk-reduced for the development of DCF-based wireless networks, such as MANETs and software-defined-radio-based cognitive ad hoc networks s.