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提出了一种新型D-RESURF埋栅SOI LDMOS(EGDR-SOI LDMOS)结构,其栅电极位于P-body区的下面,可以在扩展的埋栅电极处形成多数载流子的积累层;同时,采用DoubleRESURF技术,在漂移区中引入两区的P降场层,有效降低了器件的比导通电阻,并提高了器件的击穿电压。采用二维数值仿真软件MEDICI,对器件的扩展栅电极、降场层进行了优化设计。结果表明,相对于普通SOI LDMOS,该结构的比导通电阻下降了78%,击穿电压上升了22%。
A novel structure of the buried gate SOI LDMOS (D-RESURF SOI LDMOS) is proposed, in which the gate electrode is located below the P-body region and the accumulation layer of majority carriers can be formed at the extended buried gate electrode. At the same time, DoubleRESURF technology is adopted to introduce the P-drop field in the two drift regions to effectively reduce the specific on-resistance of the device and increase the breakdown voltage of the device. Using the two-dimensional numerical simulation software MEDICI, the extended gate electrode and the falling field layer of the device are optimized. The results show that the relative on-resistance of the structure is reduced by 78% and the breakdown voltage by 22% compared to the conventional SOI LDMOS.