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A multi-standard compatible clock and data recovery circuit(CDR) with a programmable equalizer and wide tracking range is presented.Considering the jitter performance,tracking range and chip area,the CDR employs a first-order digital loop filter,two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area.Meanwhile the tracking range is greater than ±2200 ppm,making this proposed CDR suitable for the embedded clock serial links.A test chip was fabricated in the 55 nm CMOS process.The measurements show that the test chip can achieve BER < 10~(-12)and meet the jitter tolerance specification.The test chip occupies 0.19 mm~2 with a 0.0486 mm2 CDR core,which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.
A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer and a wide tracking range is presented. Consumption of the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. While the tracking range is greater than ± 2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER <10 ~ (-12) and meet the jitter tolerance specification. The test chip occupies 0.19 mm ~ 2 with a 0.0486 mm2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb / s.