32位嵌入式RISC处理器的VLSI实现(英文)

• 作 者: 徐科 王文婷 闵昊
• 机 构: 复旦大学专用集成电路与系统国家重点实验室,复旦大学专用集成电路与系统国家重点实验室,复旦大学专用集成电路与系统国家重点实验室 上海200433,上海200433,上海200433
• 出 处: 半导体技术
• 发表日期: 2003年12期
• 关键词: RISC处理器 VLSI实现 哈佛结构 版图设计 硬件仿真 CPI MIPS 硬件验证 pipeline 冲突检测

本文实现了一个低功耗,高速度的32位RISC处理器。芯片采用了ARM V4的指令集,哈佛结构和五级流水线。同时利用了改进的流水冲突检测控制和异常处理使得流水线能以较高的速度顺序流动。与商用的ARM7TDMI相比,在0.6mm的工艺上达到了与商用0.35mm工艺制造相同的速度,同时CPI降低了26%,MIPS上升了36%。整个系统在APTIX公司提供的MP3CF硬件仿真器上完成了硬件验证,现已完成了版图设计并提交流片。

This article implements a low-power, high-speed 32-bit RISC processor. The chip uses ARM V4 instruction set, Harvard architecture and five pipeline. At the same time, the use of improved water collision detection control and exception handling make the pipeline flow at a higher speed. Compared to the commercial ARM7TDMI, the 0.6mm process achieved the same speed as the commercial 0.35mm process, while CPI was reduced by 26% and MIPS by 36%. The entire system has been hardware-verified on the MP3CF hardware emulator provided by APTIX and the layout has been finalized and submitted for streaming.