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CMOS集成电路的最大优点是低功耗.在静态的情况下,高速CMOS电路的功耗比相同功能的LSTTL电路低5至7个数量级.处于开关状态时,金属栅和高速硅栅CMOS电路的功耗正比于器件的工作频率.这是由于在工作频率越高、器件的开关次数越多的情况下,每次电压跳变均要消耗功率,所以功耗随着频率的提高而增大.本文首先讨论产生HCMOS和LSTTL电路功耗的各个因素.然后对54/74HC系列电路和LSTTL电路的功耗进行比较,最后讨论由器件的封装决定的功耗极大值.
The biggest advantage of CMOS integrated circuits is low power dissipation, and in the static case, high-speed CMOS circuits consume 5-7 orders of magnitude less power than LSTTL circuits of the same function.When switching, metal gates and high-speed Si gate CMOS circuits The power consumption is proportional to the operating frequency of the device, which is due to the fact that the higher the operating frequency, the more the switching times of the device, the more power is consumed by each voltage trip, so the power consumption increases with increasing frequency. This article first discusses the various factors that contribute to the power consumption of the HCMOS and LSTTL circuits, then compares the power consumption of the 54 / 74HC Series and LSTTL circuits, and finally discusses the power dissipation maximum determined by the package of the device.