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利用准分子激光原位淀积方法制备了BIT/PZT/BIT,PZT/BIT和BIT层状铁电薄膜,获得了电流密度-电压(I-V)回线和极化强度P-V电滞回线。在这三种结构中,Au/BIT/PZT/BIT/p-Si(100)结构的界面电位降、内建电压及频率效应是最小的。在电压转变电VT、饱和极化强度PS及矫顽场VC之间有三种关系,他们与I-V回线及P-V回线的关系相匹配,这种匹配关系使得以I-V回线操作的存储器将能够非挥发和非破坏读出及具有保持力。
The BIT / PZT / BIT, PZT / BIT and BIT layered ferroelectric thin films were prepared by excimer laser in situ deposition, and the current density-voltage (I-V) return line and the polarization-induced P-V hysteresis loop were obtained. Among the three structures, the interfacial potential of the Au / BIT / PZT / BIT / p-Si (100) structure decreases with the built-in voltage and frequency effects being the smallest. There are three relationships between the voltage transition VT, the saturation polarization PS, and the coercive field VC that match the IV loop and the PV loop such that the memory that is operated with the IV loop will be able to Non-volatile and non-destructive readout and retention.