A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy

• 作 者: 周佳 许丽丽 李福乐 王志华
• 机 构: Institute of Microelectronics, Tsinghua University,Tsinghua National Laboratory for Information Scie
• 出 处: Journal of Semiconductors
• 发表日期: 2015年08期
• 关键词: switch layout scaling conduction consuming converter analog Figure featured prot

A 10 bit,120 MS/s two-channel pipelined analog-to digital converter(ADC) is presented.The ADC is featured with improved switch by using the body effect to improve its conduction performance.A scaling down strategy is proposed to get more efficiency in the OTA’s layout design.Implemented in a 0.18-μm CMOS technology,the ADC’s prototype occupied an area of 2.05 × 1.83 mm~2.With a sampling rate of 120-MS/s and an input of4.9 MHz,the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of55.34 dB,while consuming 220-mW/channel at 3-V supply.

A 10 bit, 120 MS / s two-channel pipelined analog-to-digital converter (ADC) is presented.The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA’s layout design. Simple in a 0.18-μm CMOS technology, the ADC’s prototype occupied an area of ​​2.05 × 1.83 mm ~ 2.With a sampling rate of 120-MS / s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB while consuming 220-mW / channel at 3-V supply.