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自行设计的流水线结构ＣＭＯＳ模数转换器（Ａ／Ｄ）芯片，主要由９级流水线结构和数字校正电路组成．该设计方案采用了带源跟随器的叠式共源共栅放大器，保证了开关电容电路处理模拟信号的精度和速度；１．５位／级的转换方案减小了级间增益，使各级流水线达到较大的级间带宽；数字校正技术中借鉴了算法型Ａ／Ｄ转换器的一些经验，用一个相对简单的数字校正电路完成了预定的功能．
A self-designed pipeline CMOS analog-to-digital converter (A / D) chip, mainly by the 9-stage pipeline structure and digital correction circuit. The design uses a stacked cascode amplifier with a source follower to ensure the accuracy and speed of the switched-capacitor circuit processing the analog signal. A 1.5-bit / level conversion scheme reduces the interstage gain, The pipeline achieves a large interstage bandwidth. Digital correction technology draws on some experience of the algorithm type A / D converter and completes the intended function with a relatively simple digital correction circuit.