Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

• 作 者: 山蕊 李涛 蒋林 邓军勇 沈绪榜
• 机 构: School of Microelectronics, Xidian University,Research Center for ASIC Design, Xi’an University of P
• 出 处: Journal of Shanghai Jiaotong University(Science)
• 发表日期: 2017年04期
• 关键词: processors dynamical instruction amongst filtering distinctive register separate

The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes.Traditional reduced instruction-set computer(RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices(RCDs)consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array(RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.

The nature of dataflow computation demands the heavy flow of tokens amongst computing nodes. Traditionally reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Furthermore, computation and data management are. separated. Meanwhile, dynamical reconfiguration is accomplished ed, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.