ASIC Design of High-Speed Low-Power HDLC Controller

• 作 者: 陈禾 韩月秋
• 机 构: DepartmentofElectronicEngineering,SchoolofInformationScienceandTechnology,BeijingInstituteofTechnolo
• 出 处: Journal of Beijing Institute of Technology(English Edition)
• 发表日期: 2003年S1期
• 关键词: HDLC ASIC RS-485 BUS COMMUNICATION CONTROLLER HDLC ASIC RS-485 bus communicat

Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controllerbased on RS-485 bus is given in this paper.On principle of Top-Down design, this ASIC design usesmulti-techniques to reduce its die area and dynamic power,and