Compact-Parity Testing and Testable Design

• 作 者: XU Shi-yi
• 机 构: School of Computers
• 出 处: 东华大学学报（英文版）
• 发表日期: 2004年期
• 关键词: parity parity testing pseudo-parity testing parity testable design

Parity testing is one of the compact testing techniques,which, traditionally, relies on applying all 2n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test engineers in the past days, mainly due to the reasons of its exhaustive testing and time-consuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing: i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudoparity testable design to help realize the new way of pseudoparity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.