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为了实现宽带无线通信,提出了一种支持可变参数的准循环低密度奇偶校验码(QC-LDPC)编码器结构,在保证很高的吞吐率的前提下实现了在线可编程。该编码器采用类CPU结构,设计专用指令集,并内嵌校验矩阵存储器。将编码算法归纳为3类基本运算,设计2条专用指令就可实现任意QC-LDPC编码。通过外部总线在线配置指令和校验矩阵存储器支持多种码率码长的编码。结果表明:该结构相对于原有纯逻辑电路的结构可以在较少的资源下实现吞吐率超过1G b/s的参数可配LDPC编码。
In order to realize broadband wireless communication, a quasi-cyclic low-density parity-check code (QC-LDPC) encoder structure supporting variable parameters is proposed, which achieves on-line programmable under the premise of ensuring high throughput. The encoder uses a class CPU structure, design a dedicated instruction set, and embedded parity matrix memory. The coding algorithm can be summarized into three types of basic operations, design two dedicated instructions to achieve any QC-LDPC coding. Online Configuration of Commands and Check Matrix Memory via External Bus The memory supports a wide range of code rate code lengths. The results show that compared with the original pure logic circuit, the structure can achieve LDPC encoding with less than 1G b / s throughput.