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众所周知,工艺步骤强烈地影响MOS氧化层的辐射容限。本文介绍用离子注入法形成自对准多晶硅栅MOSFET源漏区的效果。抗辐射强度有规律地随n~+和p~+离子注入能量及掩蔽的多晶硅层厚度的变化而变化。对固定的多晶硅层厚度,存在一个使器件的性能和抗辐射特性最佳的注入能量,而其它注入能量往往会使抗辐射强度降低。这已为电容实验所证实。在总剂量为3×10~5拉德(Si)的辐射时,用这里介绍的最佳辐射加固工艺制造的n沟道器件阈值电压从-6.1V降到-1.8V。而在1×10~6拉德(Si)的辐射时,P沟道器件的阈值电压降低了4.5V。在1×10~6拉德(Si)的辐射中,8位运算器(ALU)器件仍能很好地工作。
It is well known that process steps strongly affect the radiation tolerance of MOS oxide layers. This article describes the use of ion implantation to form self-aligned polysilicon gate MOSFET source and drain regions. Radiation intensity regularly varies with n ~ + and p ~ + ion implantation energies and the masked polysilicon layer thickness. For a fixed polysilicon layer thickness, there is an implant energy that maximizes device performance and radiation resistance, while other implant energies tend to lower the radiation resistance. This has been confirmed by capacitance experiments. The threshold voltage of an n-channel device made by the best radiation-hardening process described herein is reduced from -6.1 V to -1.8 V at a total dose of 3 × 10 -5 rad (Si) radiation. The threshold voltage of P-channel devices is reduced by 4.5V at 1 × 10 ~ 6 radiated (Si) radiation. The 8-bit arithmetic unit (ALU) device still works well with 1 × 10 ~ 6 radiated (Si) radiation.