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采用SMIC 40nm CMOS工艺,设计了一种工作在10Gb/s的SerDes高速串行接口发送端电路,并创新性地提出了一种系数可调的FFE结构,使电路能适用于不同衰减的信道。电路主要模块为复接器、3阶FFE均衡器。复接器采用经典半速率结构,使用数字模块搭建,降低了功耗,并通过设计使采样时钟位于输入的最佳采样点,抑制了毛刺的产生。FFE均衡器采用结构简单的TSPC类型D触发器、低功耗的选择器和系数可调节抽头加法电路,使信号达到均衡效果,补偿信道的衰减。仿真结果显示,电路稳定工作于10Gb/s,在1.1V电源电压下功耗仅为30mW。
Using the SMIC 40nm CMOS process, a SerDes high-speed serial interface transmitter circuit operating at 10Gb / s is designed and a novel FFE structure with adjustable coefficients is proposed to make the circuit suitable for different attenuated channels. The main circuit module for the multiplexer, 3-order FFE equalizer. The multiplexer uses the classic half-rate structure, using digital modules to build, reducing power consumption, and through the design so that the sampling clock is located at the input of the best sampling points, inhibiting the generation of glitches. The FFE equalizer uses a simple TSPC type D flip-flop, a low-power selector, and a coefficient-adjustable tap adder circuit to balance the signal and compensate for channel fading. The simulation results show that the circuit is stable at 10Gb / s and consumes only 30mW at 1.1V supply voltage.