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提出了一种用于20bitΣ-Δ数模转换器中的内插滤波器的有效实现方法,内插滤波器的过采样率为128.该方法使用多级结构以降低滤波器系数的复杂度和有限字长效应.同时提出了基于系数混合基分解的多相半带滤波器的无乘法器实现方法,它降低了控制逻辑的复杂程度,并大大节省了芯片面积.芯片采用0.13μm CMOS工艺实现,整个插值滤波器面积小于0.63mm2.整个电路系统仅用简单的硬件单元实现,且结构规整,这有利于大规模集成电路制造,并可应用于高精度数据转换电路中.
An effective implementation of an interpolation filter for a 20-bit sigma-delta digital-to-analog converter is presented, with an oversampling rate of 128. This method uses a multistage structure to reduce the complexity of the filter coefficients and Finite word length effect.At the same time, a multi-phase half-band multiplier-less multiplier method based on coefficient mixed basis decomposition is proposed, which reduces the complexity of the control logic and greatly saves the chip area.The chip is implemented with 0.13μm CMOS technology , The entire interpolation filter area of less than 0.63mm2. The entire circuit system with only a simple hardware unit to achieve, and structured, which is conducive to large-scale integrated circuit manufacturing, and can be applied to high-precision data conversion circuit.