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We present an input/output block(IOB) array used in the radiation-hardened SRAM-based fieldprogrammable gate array(FPGA) VS1000,which is designed and fabricated with a 0.5μm partially depleted silicon-on-insulator(SOI) logic process at the CETC 58th Institute.Corresponding with the characteristics of the FPGA,each IOB includes a local routing pool and two IO cells composed of a signal path circuit,configurable input/output buffers and an ESD protection network.A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels.The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic.Radiation-hardened designs,including A-type and H-type body-tied transistors and special D-type registers,improve the anti-radiation performance.The ESD protection network,which provides a high-impulse discharge path on a pad,prevents the breakdown of the core logic caused by the immense current.These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs.The functionality and performance of the IOB array is proved after a functional test.The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si),a dose survivability rate of 1.5×10~(11) rad(Si)/s,and a neutron fluence immunity of 1×10~(14)n/cm~2.
It is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Coacted with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input / output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input / output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL / CMOS standard levels. local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. these design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad (Si), a dose survivability rate of 1.5 × 10-11 rad (Si ) / s, and a neutron fluence immunity of 1 × 10 ~ (14) n / cm ~ 2.