论文部分内容阅读
As interconnects shrink beyond 90nm node, the presence of etch residues can create high via resistance and void nucleation during stress migration (SM) testing. Physical Ar+ preclean is effective in removing residues, but early SM failures have been seen due to Cu resputter from underlying trenches. Reactive preclean methods show promise in reducing CuOx and cleaning Si, N, F, C, O etch residues in presence of H+, H* species. In this paper, reactive preclean and PVD PunchThru process (deposit-etch-deposit) is proposed as solution to conventional PVD. The PunchThru process reduces via resistance, improves SM and protects dual-damascene bevel and unlanded vias from Cu diffusion by presence of thin Ta deposition step. In addition, the U-shaped interface, which minimizes electron crowding and localized heating effects, increases the mean time to failure by electromigration. Consistent, repeatable blanket film property and good parametric electrical test results have proven the production worthiness of this process.