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本文提出一个适应调试功能的ＶＨＤＬ模型及ＶＨＤＬ模拟算法──ＶＳＩＭ．它与可视化ＶＨＤＬ原理图输入工具ＶＤＥＳ和高级图形调试器ＶＤＢＸ结合在一起，为设计者检查、修改自己的设计提供了极大的便利．该模拟器采用层次式结构行为混合模型，保存ＶＨＤＬ描述的所有信息和结构，以利于实现调试功能．模拟算法采用基于进程的事件驱动算法及层次式模块调用算法，并提供模拟时间、语句行、模块（包括元件、进程和子程序）、信号／变量、条件等各种中断类型并能继续模拟．
This paper presents a VHDL model to adapt to debug capabilities and VHDL simulation algorithm ─ ─ VSIM. It is combined with the visual VHDL schematic input tool VDES and the advanced graphics debugger VDBX to provide great convenience for designers to inspect and modify their designs. The simulator uses hierarchical structural behavioral mixed model to save all the information and structure described by VHDL in order to facilitate the debugging function. The simulation algorithm uses a process-based event-driven algorithm and a hierarchical module calling algorithm and provides simulation time, statement lines, modules (including components, processes and subroutines), signals / variables, conditions and other interrupt types and can continue to simulate.