A 0.35μm CMOS 6.1GHz 1∶4 Static Frequency Divider

• 作 者: 陆建华
• 机 构: Institute of RF-& OE-ICs Southeast University, Nanjing 210096, P.R.China
• 出 处: High Technology Letters
• 发表日期: 2003年02期
• 关键词: PECL circuits

A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1∶2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.

A 1: 4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1: 2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. traditional results of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1: 2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.