互连延迟的分析方法

• 作 者: 郑赟 候劲松 刘昆 黄道君
• 机 构: 北京中电华大电子设计有限责任公司,北京中电华大电子设计有限责任公司,西安电子科技大学机电工程学院,西安电子科技大学机电工程学院,
• 出 处: 中国集成电路
• 发表日期: 2003年10期
• 关键词: 门延迟 深亚微米 冲激响应 端结点 瞬态 概率分布函数 漏电阻 评估分析 分析方法 阶跃响应

随着工艺技术到达深亚微米领域,互连线的延迟影响越来越大,已经超过门延迟,成为电路延迟的主要部分。因此,互连线的延迟已成为集成电路设计中必须解决的问题。目前人们已展开了全面、深入地研究,提出了许多方法。本文将介绍各类互连延迟的评估分析方法,分析它们的原理,比较它们的优缺点,指出它们的适用范围。

As technology reaches deep-submicron fields, the latency of interconnects is increasingly affected by the delay of the gate, becoming a major part of the circuit delay. Therefore, the latency of interconnects has become a problem that must be addressed in the design of integrated circuits. At present, people have conducted a comprehensive and in-depth study, put forward many methods. This article will introduce various methods of evaluation of interconnect delay, analyze their principles, compare their strengths and weaknesses, and point out their scope of application.