Design and realization of a high productivity cluster-based network application reconfigurable accel

• 作 者: 曾宇
• 机 构: National High Performance Computer Engineering Technology Center,Beijing 100089,P.R.China Graduate S
• 出 处: High Technology Letters
• 发表日期: 2008年02期
• 关键词: accelerator realization accel programmable processor submitted ordinary filterin

Improving processor frequency to strengthen massive data processing capability will lead to incremen-tal server marginal costs and bring about a series of problems such as power consumption,managementcomplexity,etc.Based on the field programmable gate array(FPGA),TCP offload engine(TOE),zero-copy and other key technologies,this paper describes the design and realization of a reconfigurable accel-erator board.In this board,TCP/IP protocol will be moved to high-speed reconfigurable acceleratorboard.The packets will be labeled according to the protocol and submitted to the upper data processingsoftware after IP-quintuple filtering in hardware.Reconfigurable accelerator board obtains higher perfor-mance speed-up compared with ordinary NIC card.

Improving processor frequency to strength massive data processing capability will lead to incremen-tal server marginal costs and bring about a series of problems such as power consumption, management complexity, etc. Based on the field programmable gate array (FPGA), TCP offload engine (TOE ), zero-copy and other key technologies, this paper describes the design and realization of a reconfigurable accel-erator board. In this board, TCP / IP protocol will be moved to high-speed reconfigurable acceleratorboard. The packets will be labeled according to the protocol and submitted to the upper data processingsoftware after IP-quintuple filtering in hardware. Reconfigurable accelerator board obtains higher perfor-mance speed-up compared with ordinary NIC card.