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Area-efficient design methodology is proposed for the analog decoding implementations of the rate-1/2 accumulate repeat-4 jagged-accumulate (AR4JA) low density parity check (LDPC) code.The proposed approach is designed using optimized decoding architecture and regularized routing network,in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved.The prototyping chip used to verify the approach is fully integrated in a four-metal double-poly 0.35 μm complementary metal oxide semiconductor (CMOS) technology,and includes an input-output interface that maximizes the decoder throughput.The decoding core area is 2.02 mm2 with a post-layout area utilization of 80％.The decoder was successfully tested at the maximum data rate of 10 Mbit/s,with a core power consumption of 6.78 mW at 3.3 V,which corresponds to an energy per decoded bit of 0.677 nJ.The proposed analog LDPC decoder with low processing power and high-reliability is suitable for space-and power-constrained spacecraft system.