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为了减少大素数生成时间并加快RSA(Rivest,Shamir&Adleman)公钥密码算法的加解密速度,并行化实现了小素数试除和Miller-Rabin素性测试两大关键步骤,使其在进行素性测试的同时能进行小素数试除,从而大幅减少了小素数试除单独运算消耗的时间.为了加速Miller-Rabin素性测试须要反复调用的模乘运算单元,采用一种基于字的高基Montgomery算法及多级流水结构,设计了一种可配置的高速模乘运算电路.经FPGA(现场可编程门阵列)测试,在100 MHz频率下,生成的512bit大素数的平均耗时约为75ms,生成的1 024bit密钥对的平均耗时约为166ms,耗时只有参照结果的54.2%左右.
In order to reduce the generation time of large primes and speed up the encryption and decryption of RSA (Rivest, Shamir & Adleman) public-key cryptosystem, the two key steps of low-prime test and Miller-Rabin test are implemented in parallel, Can reduce the number of prime primes test, which significantly reduces the number of small prime test time consumed alone.In order to speed up the Miller-Rabin prime test requires repeated call modular operation unit, using a word-based high-base Montgomery algorithm and multi-level The design of a configurable high-speed modular multiply operation circuit.The FPGA (Field Programmable Gate Array) test, at 100 MHz frequency, generated 512-bit large prime average time-consuming about 75ms, the generated 1 024bit The average time spent on the key pair is about 166 ms, consuming only about 54.2% of the reference.