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本文研究了采用氧化物隔离工艺的高速低功耗肖特基晶体 管-晶体管 逻辑(TTL)电路。在此工艺中,晶体管被氧化物所包围着。特别是由于采用发射极的四个边中相对应的两边与氧化墙相邻接的隔离结构,所以能够缩小晶体管的尺寸,减小寄生电容。同时,由于采用了浅结结构,因而获得的电流增益·带宽乘积f_T为5千兆赫。电路方面,在原来的肖特基TTL电路基础上增加了一级放大,构成了三级结构。输入元件采用了二极管。因此,提高了电路的噪声容限。采用此工艺的肖特基电路系列的速度比以往的低功耗肖特基TTL电路快75％、功耗为标准肖特基TTL电路的1/4。
In this paper, a high-speed, low-power Schottky transistor-transistor logic (TTL) circuit using oxide isolation technology has been investigated. In this process, the transistor is surrounded by oxide. In particular, since the isolation structure in which the corresponding two sides of the four sides of the emitter are adjacent to the oxidation wall is used, the size of the transistor can be reduced and the parasitic capacitance can be reduced. At the same time, the gain-bandwidth product of the current gain f_T is 5 gigahertz because of the shallow junction structure. Circuit, in the original Schottky TTL circuit based on an increase of amplification, constitute a three-tier structure. Input components using a diode. Therefore, the noise margin of the circuit is increased. The SCHOTTKY circuit family that uses this process is 75% faster than previous low-power Schottky TTL circuits and consumes a quarter of the power of standard Schottky TTL circuits.