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本文提出适用于短沟道薄膜全耗尽SOI器件的大信号电容模型。该模型除考虑了SOI短沟道器件中出现的速度饱和效应、DIBL效应及源漏耗尽层电荷分享效应外,还包括了SOI器件中特有的膜厚效应、正背栅耦合效应等对电容特性的影响。通过与体硅器件的二维模拟和实测电容特性以及已报道的薄膜SOI器件电容模型相比较可知,本文模型可较好地描述短沟道SOI器件的电容特性。另外,所建电容模型形式简洁,参数提取方便,因而可做为薄膜全耗尽SOI器件大信号电容模型移植到电路模拟程序(如SPICE)之中。
This paper presents a large signal capacitance model suitable for short-channel thin film fully depleted SOI devices. The model not only considers the speed saturation effect, DIBL effect and depletion layer charge-sharing effect of SOI short-channel devices, but also includes the effects of film thickness, the back-gate coupling effect and so on on the capacitance Effect of characteristics. Compared with the two-dimensional simulation and measured capacitance characteristics of bulk silicon devices and the reported capacitance model of thin-film SOI devices, the model in this paper can better describe the capacitance characteristics of short-channel SOI devices. In addition, the built-in capacitance model has the advantages of concise form and convenient parameters extraction, so it can be transplanted into the circuit simulation program (such as SPICE) as the thin-film SOI device large signal capacitance model.