论文部分内容阅读
一个大规模集成的4位互补对称MOS(COS/MOS)并行处理片已经产生,它具有计算机运算器4位部分的能力。并行处理片有4位运算处理和全功能译码存贮的能力、扩展能力和数码引线的时间分配。这个阵列有27个输入输出引线,等值于200个双输入门的逻辑复杂性,装配在含有775个有源器件的146×155密耳的片子上。此外,可以通过外部引线的连结使逻辑在电学上可变,以使阵列适应作为大型运算处理机4位部分的功能。为了便于制成一个实用尺寸的阵列,大多注意于使用功能门、传送门和布版效率以实现器件小型化。应用4个并行处理片的16位加法时间,最坏情况是2.8微秒。在250千周工作频率下,阵列的功耗是10毫瓦。因此,阵列代表着一个低功率中速逻辑元件,也是中央处理机重复运用的基本单元。
A massively integrated 4-bit complementary symmetric MOS (COS / MOS) parallel processing chip has been created that has the capability of a 4-bit portion of a computer operator. Parallel processing chip has 4 computing operations and full-featured decoding storage capacity, scalability and digital lead time allocation. This array has 27 I / O pins, equivalent to the logic complexity of 200 dual input gates, mounted on a 146 × 155 mil film with 775 active devices. In addition, the logic can be electronically variable through the connection of external leads to adapt the array to function as a 4-bit portion of a large computing processor. In order to facilitate the formation of a practical size array, most of the attention to the use of functional doors, portal and layout efficiency to achieve device miniaturization. Using 16 parallel additions of 4 parallel processing slices, the worst case is 2.8 microseconds. The array consumes 10 milliwatts at 250 kilohertz operating frequency. Therefore, the array represents a low-power medium-speed logic components, but also the basic unit of the central processing unit for repeated use.