An 11-bit ENOB,accuracy-programmable,and non-calibrating time-mode SAR ADC

• 作 者: 樊华 韩雪 魏琦 杨华中
• 机 构: Division of Circuits and Systems,Department of Electronic Engineering,Tsinghua University,
• 出 处: Journal of Semiconductors
• 发表日期: 2013年01期
• 关键词: programmable SFDR nonlinearity Nyquist offset capacitor distortion register conv

A 10 or 12 bit programmable successive approximation register(SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio(SNDR) of 68 dB(11 ENOB),a spurious free dynamic range(SFDR) of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity(DNL) and integral nonlinearity(INL) are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.

A 10 or 12 bit programmable two approximation register (SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented. Techniques for improving the accuracy of time-domain comparators are presented. The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC. Prototyped in a 0.18-m, 6M1P CMOS process, the ADC, at 12 bit, 100 kS / s, achieves a Nyquist signal-to-noise-plus- distortion ratio 68 dB (11 ENOB), spurious free dynamic range (SFDR) of 77.48 dB, while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.2 / -0.74 LSB and C1 .27 / -0.97 LSB, respectively.