【摘 要】
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Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging
【机 构】
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National High Performance IC Shanghai Design Center, Shanghai 201204, China
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Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi core ISS (MCISS) is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the save and restore mechanism, the verification procedure and the debugging are speeding up greatly.
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