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使用Verilog HDL硬件描述语言完成了对CAN总线控制器的设计,能够实现符合CAN2.0A协议的所有功能。本总线控制器的外部接口采用Altera公司开发的Avalon总线接口,增强了控制器的应用灵活性。本设计使用Modelsim软件完成了功能仿真和时序仿真。
Using Verilog HDL hardware description language to complete the CAN bus controller design, to achieve all the features in line with CAN2.0A protocol. The bus controller’s external interface using Altera’s Avalon bus interface developed to enhance the controller’s application flexibility. The design uses Modelsim software to complete the functional simulation and timing simulation.