具有信道估计功能的Viterbi软判决译码器的FPGA实现

• 作 者: 王培 王群生
• 出 处: 广东通信技术
• 发表日期: 2005年04期
• 关键词: Viterbi Viterbi算法 信道 软判决译码 信道状况 译码器 信道估计 溢出 卷积码 仿真环境

Viterbi算法在码率和约束度不大的情况下易于硬件实现,而且复杂度不是主要问题。采用基于译码原理实现的算法,通过VHDL对FPGA进行编程,在Xilinx公司的ModelSimde仿真环境下实现了卷积码的Viterbi软判决译码.同时FPGA可根据译码输出反馈在一定限度内估计信道状况,计算得出误比特个数,调整所使用的比特度量表,为信道均衡提供参考,达到适应信道状况变化的目的。另外在FPGA的设计仿真过程中还注意到了寄存器溢出问题。

The Viterbi algorithm is easy to implement in hardware with low bit-rate and constraint, and complexity is not a major issue. The algorithm based on the decoding principle is used to program the FPGA through VHDL, and the Viterbi soft decision decoding of the convolutional code is realized under the ModelSimde simulation environment of Xilinx.At the same time, the FPGA can estimate the channel within a certain limit according to the decoding output feedback Status, calculate the number of bit errors, adjust the used bit metrics to provide a reference for channel equalization, to adapt to changes in channel conditions. Also in the FPGA design simulation process also noted the problem of register overflow.