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所述逻辑设计有三个特点: 1.提出只用一枚半加器来构成位运算器。 2.提出一个快速移位方案,可以在一次字周期中左移或右移任意位。 3.提出一个简单灵活的内部数据总线结构,从而简化阵列基本单元(PE)的设计,并使之更适应大规模集成电路(LSI)的工艺要求。设计是针对N-MOS大规模集成电路进行的,当主频为2MHZ,字长16位时,一个32×32PE阵列系统的最高运算速度为:每秒可进行六千万次传送操作;五千万次左移或右移任意位操作;四千万次定点加减法或其他逻辑运算;一千万次浮点加法(阶码5位);二百八十万次定点乘法(双倍字长乘积);二百四十万次浮点乘法。假如阵列中平均有一半PE空闲时,则上述操作次数将减半。
The logic design has three characteristics: 1. It is proposed that only one half adder be used to form the bit operator. 2. Propose a fast shift scheme, you can shift left or right in any word cycle a bit. 3. A simple and flexible internal data bus structure is proposed, which simplifies the design of the array basic unit (PE) and makes it more suitable for large scale integrated circuit (LSI) process requirements. The design is for N-MOS large scale integrated circuits. When the clock speed is 2MHZ and the word length is 16 bits, the maximum operation speed of a 32 × 32PE array system is as follows: 60 million transmission operations per second; 40,000 left-shift or right-shift arbitrarily; 40 million fixed-point addition and subtraction or other logic operations; 10 million floating-point additions (5 steps); 2.8 million fixed-point multiplications Long product); 2.4 million floating point multiplication. If on average half of the arrays in the PE are idle, the number of operations will be halved.