【摘 要】
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From microelectronics to nano-electronics,the surface and interface properties of materials and devices are more and more important,comparing to the bulk properties.Manufacturing under ultra-clean roo
【机 构】
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Suzhou Institute of Nano-Tech and Nano-Bionics(SINANO),CAS
论文部分内容阅读
From microelectronics to nano-electronics,the surface and interface properties of materials and devices are more and more important,comparing to the bulk properties.Manufacturing under ultra-clean rooms eventually could not prevent contaminations from O2,C,and H2O-vapor,during wafer transferring through air,which are very critical to improving the nano-devices performance and reliability.For example,the two major challenges of GaN-based HEMT power devices are off-current leaking and dynamic-current collapse,and the root causes are believe to be related to the interfacial defects or impurities.The best solution of eliminating these unfavorable issues is to process the wafers in a well-controlled environment,without exposure wafers to air during the whole process flow.At present,a vacuum-interconnected R&D facility is being built at Suzhou Institute of Nano-tech and Nano-bionics,CAS,which links more than 30 processing and characterization tools through UHV tubes with a diameter of 150 millimeters and total length of 100 meters.Therefore,it is possible to integrate critical processes together under a vacuum environment,and avoid any uncontrollable contaminations on wafer surfaces during wafer transfer between processing steps.This newly developed technology will not only largely reduce the process steps but also greatly enhance the device performance.In additional,there are also in-line characterization and analytical tools connected to the system,which are very necessary and useful to study the material intrinsic properties and processing mechanisms.This talk will focus on the advantages of vacuum-interconnected technology and its applications on researches,developing and fabrications of advanced Ⅲ-Ⅴ semiconductor nano-devices.
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