论文部分内容阅读
文章研究了在ＧａＡｓ工艺、双层金属布线、基于门阵的宏元胞模式下，采用时间驱动算法布局设计（ＴｉｍｉｎｇＤｒｉｖｅｎＰｌａｃｅｍｅｎｔ）的布线算法。算法以芯片性能得到最大限度的改善，包括芯片关键路径时延最短、互连线总长最短、最长互连线最短、布线密度均匀等为目标，从而达到超高速的目的。
In this paper, the routing algorithm based on time-driven algorithm layout design (TimingDrivenPlacement) is studied in GaAs process, double-layer metal wiring, and gate cell based macro cell mode. The algorithm achieves the maximum improvement of the chip performance, including the shortest key path delay of the chip, the shortest interconnection length, the shortest interconnection length and the uniform wiring density, so as to achieve the purpose of ultra-high speed.