On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit

• 作 者: ZHANGJingkai[1]ChungLenLee[2]TIANChao[1]YUFei[1]
• 机 构: Institute of Microelectronics,Peking University Shenzhen Graduate School Shenzhen 518055,China
• 出 处: 第十二届全国容错计算学术会议
• 发表日期: 2007年期

This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier occillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the circuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 urn process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks.