A Hybrid Aging Delay Model Considering PBTI and TDDB

• 作 者: YongMiao;MaoxiangYi;GuimaoZhang;DawenXu;
• 机 构: School of Electronic Science and Applied Physics Hefei University of Technology Hefei,Anhui Province
• 出 处: 中国电子学会电路与系统学会第二十五届年会
• 发表日期: 2014年期

　　Below 45nm process technique,the shrinking silicon feature size brings in high-k/metal gate which significantly exacerbates the Positive Bias Temperature Instability (PBTI) and Time-Dependent Dielectric Breakdown (TDDB) effect of NMOS transistor.However,previous works presented delay models to characterize PBTI or TDDB individually.This paper demonstrates that the delay caused by joint effect of PBTI and TDDB widely differs from the cumulated result of the delay caused by PBTI and TDDB respectively with the experiments on an inverter chain.This paper proposes a hybrid aging delay model comprising both PBTI and TDDB effect by analyzing the relationship between aging propagation delay and inherent delay of the gate.Experimental results on the logic gates under 45nm,32nm,22nm and 16nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%,meanwhile the average error is about 1.5%.