论文部分内容阅读
Throughout its twenty-five year history,logic emulation architectures have been governed by Rents Rule.This empirical observation,first used to build 1960s mainframes,predicts the average number of cut nets that result when a digital module is arbitrarily partitioned into multiple parts,such as the FPGAs of a logic emulator.A fundamental advantage of emulation is that,unlike most devices,FPGAs always grow in capacity according to Moores Law,just as the designs to be emulated have grown.Unfortunately packaging technology advances at a far slower pace,leaving emulators short on the pins demanded by Rents Rule.Many cut nets are now sent through each package pin,which costs speed,power and area.At todays system-on-chip level of design,the number of system-level modules is growing,while their sizes are remaining constant.In the meantime,FPGAs have grown from a handful of logic lookup tables(LUTs)at the beginning to over a million LUTs today.At this scale,an entire system-level module such as an advanced 64-bit CPU can fit inside a single FPGA.Fewer module-internal nets need be cut,so Rents Rule constraints are relaxing.Fewer and higher-level cut nets means logic emulation with megaLUT FPGAs is becoming faster,cooler,smaller,cheaper,and more reliable.FPGAs Moores Law scaling is escaping from Rents Rule.