【摘 要】
：
In this paper we address the issue of designing the detailed architectures of FPGAs,which have a great impact on the overall performances of an FPGA in practice.Firstly,a novel FPGA architecture descr
【机 构】
：
University of Chinese Academy of Sciences;System on Programmable Chip Research Department,Institute
【出 处】
：
The 4th International Workshop on Advanced Technologies in P
论文部分内容阅读
In this paper we address the issue of designing the detailed architectures of FPGAs,which have a great impact on the overall performances of an FPGA in practice.Firstly,a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML.This format permits the description of any detailed architecture of hard blocks and channels.Then we present a general algorithm of building FPGA resource graph.The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system that we developed to enable detailed architecture design.Experimental results show that a maximum of 16.36%reduction in total wirelength and a maximum of 9.34%reduction in router effort can be obtained by making very little changes to detailed architectures,which proves the necessity and effectiveness of our model.
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