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本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。分解过程利用单元库函数真值矩阵及各分解部分用标准单元实现的难易程度、逻辑级数来评价、引导分解得到的多级逻辑易于用标准单元组合实现。使用的标准单元类型具有较大程度的相似性,有利于基于标准单元布局布线软件进一步减少芯片面积。
This paper proposes a multi-level logic function decomposition technique based on standard cell library in ASIC synthesis technology. The decomposition process utilizes the truth matrix of the cell library functions and the degree of difficulty and logic progression achieved by the standard cells in each decomposition part. The multi-level logic obtained through the guidance decomposition is easy to be implemented by combining standard cells. The use of standard cell types has a greater degree of similarity and facilitates further reduction of chip area based on standard cell layout software.